A review of III-V Tunnel Field Effect Transistors for future ultra low power digital/analog applications

被引：16

作者：

Saravanan, M. ^{[1
,2
]}

Parthasarathy, Eswaran ^{[1
,3
]}

机构：

[1] Dept Elect & Commun Engn, Chennai, Tamil Nadu, India

[2] Sri Eshwar Coll Engn, Coimbatore, Tamil Nadu, India

[3] SRM Inst Sci & Technol, Chennai, Tamil Nadu, India

来源：

MICROELECTRONICS JOURNAL | 2021年 / 114卷

关键词：

Ambipolarity; Bandgap engineering; Band to band tunneling (BTBT); Gate engineering; III-V materials; Nanowires; DRAIN CURRENT MODEL; PERFORMANCE ENHANCEMENT; ANALOG/RF PERFORMANCE; HETEROJUNCTION TFET; HIGH-SPEED; SRAM CELL; GATE; FET; CHANNEL; INAS;

D O I：

10.1016/j.mejo.2021.105102

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Tunnel Field Effect Transistors (TFETs) have emerged as serious contenders for the replacement of traditional MOSFET technology for the future ultra low power Analog/Digital circuit applications because of their unique properties such as Sub-60 mV/decade subthreshold swing (SS), negligible short channel effects (SCEs) and very low off current (IOFF). This review article intensively studies the RF/Analog and DC performance of III-V materials based TFETs. This article highlights the scalability of III-V TFETs, influence of thickness and permittivity of gate dielectric, interface trap density, other geometrical dimensions, material properties and various TFET architectures on the ON and OFF state performance of III-V TFETs. This paper also point outs the impact of temperature, strain, gate metal work function, source-gate overlap and underlap, doping concentration and supply voltage scaling on the DC, RF/Analog characteristics of III-V TFETs.

引用

页数：26

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