Modeling the Overshooting Effect of Multi-input Gate in Nanometer Technologies

被引：0
|
作者：
Ding, Li [1 ]
Huang, Zhangcai [2 ]
Jiang, Minglu [1 ]
Kurokawa, Atsushi [3 ]
Inoue, Yasuaki [1 ]
机构：
[1] Waseda Univ, Grad Sch Informat Prod & Syst, Wakamatsu Ku, 2-7 Hibikino, Kitakyushu, Fukuoka 8080135, Japan
[2] Fukuoka Ind Sci & Technol Fdn, Sawara Ku, Fukuoka 8140001, Japan
[3] Hirosaki Univ, Grad Sch Sci & Technol, Hirosaki, Aomori 0368561, Japan
来源：
2011 IEEE 54TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS) | 2011年
关键词：
CMOS INVERTER DELAY;
D O I：
暂无
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
With the advent of nanometer age in digital circuits, the overshooting time becomes a dominating component of gate delay for CMOS logic gates. Till now, few researches have focused on the overshooting effect of multi-input gate. Therefore, in this paper, an effective model considering the overshooting effect of multi-input gate is presented. The experimental results using 32nm PTM model reflect that the proposed model is accurate within 3.6% error compared with SPICE simulation results.
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页数：4
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