Building Neural Network Synapses Based on Binary Memristors

The design of an analog multilevel memory cell based on the use of resistors and binary memristors is proposed. This design provides a greater number of resistance levels with a smaller number of elements than the well-known multilevel memory devices. The cell is designed to set the synapse weights in hardware-implemented neural networks. The neuron vector of weights can be represented by a crossbar of binary memristors and a resistor set. An algorithm is proposed for mapping the neuron weight to the proposed multilevel memory cell. The proposed approach is illustrated by the construction example of a neuron for partitioning a set of vectors into two classes.