An advanced flash memory technology on SOI

被引：5
|
作者：
Burnett, D [1 ]
Shum, D [1 ]
Baker, K [1 ]
机构：
[1] Motorola Inc, NVM Technol Ctr, Austin, TX 78721 USA
来源：
INTERNATIONAL ELECTRON DEVICES MEETING 1998 - TECHNICAL DIGEST | 1998年
关键词：
D O I：
10.1109/IEDM.1998.746519
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
For the first time, EEPROM functionality is demonstrated on double-poly bitcells on SOI using the same layout as standard bulk CMOS bitcells. By using FN tunneling for program and erase (P/E) operations, the P/E characteristics of the floating-body SOI bitcell are comparable to the bulk CMOS characteristics. Bitcell endurance for SOI cells show significantly less window closure than bulk CMOS cells. High-voltage SOI device characteristics are also compared with bulk devices. With sufficient body contacts, the high-voltage SOI devices can support the required bitcell voltages.
引用
收藏
页码：983 / 986
页数：4
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