A Survey on Efficient Convolutional Neural Networks and Hardware Acceleration

被引:85
|
作者
Ghimire, Deepak [1 ]
Kil, Dayoung [1 ]
Kim, Seong-heum [1 ]
机构
[1] Soongsil Univ, Coll Informat Technol, Sch AI Convergence, Seoul 06978, South Korea
基金
新加坡国家研究基金会;
关键词
deep learning; compression and acceleration; pruning; quantization; network architecture search; ARCHITECTURE; PROCESSOR;
D O I
10.3390/electronics11060945
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
Over the past decade, deep-learning-based representations have demonstrated remarkable performance in academia and industry. The learning capability of convolutional neural networks (CNNs) originates from a combination of various feature extraction layers that fully utilize a large amount of data. However, they often require substantial computation and memory resources while replacing traditional hand-engineered features in existing systems. In this review, to improve the efficiency of deep learning research, we focus on three aspects: quantized/binarized models, optimized architectures, and resource-constrained systems. Recent advances in light-weight deep learning models and network architecture search (NAS) algorithms are reviewed, starting with simplified layers and efficient convolution and including new architectural design and optimization. In addition, several practical applications of efficient CNNs have been investigated using various types of hardware architectures and platforms.
引用
收藏
页数:23
相关论文
共 50 条
  • [1] Efficient Hardware Acceleration of Convolutional Neural Networks
    Kala, S.
    Jose, Babita R.
    Mathew, Jimson
    Nalesh, S.
    [J]. 32ND IEEE INTERNATIONAL SYSTEM ON CHIP CONFERENCE (IEEE SOCC 2019), 2019, : 191 - 192
  • [2] Efficient Hardware Acceleration of Sparsely Active Convolutional Spiking Neural Networks
    Sommer, Jan
    Ozkan, M. Akif
    Keszocze, Oliver
    Teich, Juergen
    [J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2022, 41 (11) : 3767 - 3778
  • [3] Binarized Convolutional Neural Networks with Separable Filters for Efficient Hardware Acceleration
    Lin, Jeng-Hau
    Xing, Tianwei
    Zhao, Ritchie
    Zhang, Zhiru
    Srivastava, Mani
    Tu, Zhuowen
    Gupta, Rajesh K.
    [J]. 2017 IEEE CONFERENCE ON COMPUTER VISION AND PATTERN RECOGNITION WORKSHOPS (CVPRW), 2017, : 344 - 352
  • [4] Compressing Sparse Ternary Weight Convolutional Neural Networks for Efficient Hardware Acceleration
    Wi, Hyeonwook
    Kim, Hyeonuk
    Choi, Seungkyu
    Kim, Lee-Sup
    [J]. 2019 IEEE/ACM INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN (ISLPED), 2019,
  • [5] Optimization and acceleration of convolutional neural networks: A survey
    Habib, Gousia
    Qureshi, Shaima
    [J]. JOURNAL OF KING SAUD UNIVERSITY-COMPUTER AND INFORMATION SCIENCES, 2022, 34 (07) : 4244 - 4268
  • [6] An Updated Survey of Efficient Hardware Architectures for Accelerating Deep Convolutional Neural Networks
    Capra, Maurizio
    Bussolino, Beatrice
    Marchisio, Alberto
    Shafique, Muhammad
    Masera, Guido
    Martina, Maurizio
    [J]. FUTURE INTERNET, 2020, 12 (07):
  • [7] Design of Convolutional Neural Networks Hardware Acceleration Based on FPGA
    Qin, Huabiao
    Cao, Qinping
    [J]. Dianzi Yu Xinxi Xuebao/Journal of Electronics and Information Technology, 2019, 41 (11): : 2599 - 2605
  • [8] Design of Convolutional Neural Networks Hardware Acceleration Based on FPGA
    Qin Huabiao
    Cao Qinping
    [J]. JOURNAL OF ELECTRONICS & INFORMATION TECHNOLOGY, 2019, 41 (11) : 2599 - 2605
  • [9] A Configurable and Versatile Architecture for Low Power, Energy Efficient Hardware Acceleration of Convolutional Neural Networks
    Christensen, Steinar Thune
    Aunet, Snorre
    Qadir, Omer
    [J]. 2019 IEEE NORDIC CIRCUITS AND SYSTEMS CONFERENCE (NORCAS) - NORCHIP AND INTERNATIONAL SYMPOSIUM OF SYSTEM-ON-CHIP (SOC), 2019,
  • [10] An Efficient Reconfigurable Hardware Accelerator for Convolutional Neural Networks
    Ansari, Anaam
    Gunnam, Kiran
    Ogunfunmi, Tokunbo
    [J]. 2017 FIFTY-FIRST ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS, AND COMPUTERS, 2017, : 1337 - 1341