A novel single-ended 9T FinFET sub-threshold SRAM cell with high operating margins and low write power for low voltage operations

Recently, SRAM for sub-threshold operation is in developing stage for ultra-low power applications and portable devices. It aims to support high operating margins and high performance with low power applications under process and temperature variations. In this paper, a novel FinFET based 9T SRAM cell is proposed, which employs single ended bit-line scheme to perform read and write operations in the near-threshold region, without any boosted power supply and write assist circuitry. The write-ability, write power and write time have been improved by breaking down the feedback of two cross-coupled inverter pairs using both transistors (M4 and M5) to cut off at write mode, thereby obviating write as well as read constraints on semiconductor device dimensions. Apart from this, write-ability and write time improved substantially by using low threshold voltage (V-t) transmission gate as an access transistor. The read time and read margin have also improved by separate low V-t decouple read transistor (M9). The different characteristics are compared at 7 mu, 10 nm, 14 nm, 16 nm, and 20 nm in HSPICE at 0.5 V-dd. Furthermore, the various cell parameters are investigated at voltages from 0.3 to 0.9 V and at a temperature range of 35 to 100 degrees C. The experimental results show that proposed 9T cell achieves 1.86 x and 1.06 x better write-ability as compared to 7T cell and 8T cell respectively. The read stability is 2.56 x of 7T and 1.05 x of 8T. The data retention ability is 1.57x of 7T and 1.05x of 8T. The write power is 30.49% of 8T and 5.01% of a 7T. In addition, it takes 3.57x and 1.77x less write time when compared to 8T cell and 7T cell respectively at 0.5 V using 20 nm process technology.