A fully integrated spread spectrum clock generator using a dual-path loop filter

被引：0

作者：

Kao, Yao-Huang ^{[1
]}

Hsieh, Yi-Bin ^{[1
]}

机构：

[1] Natl Chiao Tung Univ, Inst Commun Engn, Hsinchu 30050, Taiwan

来源：

IEEE MWSCAS'06: PROCEEDINGS OF THE 2006 49TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II | 2006年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A fully integrated spread spectrum clock generator (SSCG) using the VCO direct modulation was presented. The dual-path loop filter in the phased locked loop was employed to reduce the required area of capacitance in the filter by using another charge pump circuit. In the meantime, the third charge pump was used to achieve the triangle modulation. The proposed circuit had been fabricated by TSMC 0.35um CMOS single-poly quadruple-metal process. The clock rate from 50MHz to 480MHz with center spread spectrum ratios with 0.5%-2% was verified. The size of chip area was 0.82xO.8mm(2) including the loop filter and the power consumption was 27.5mW at 400MHz.

引用

页码：7 / +

页数：2

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