A study of predictable execution models implementation for industrial data-flow applications on a multi-core platform with shared banked memory

被引：4

作者：

Schuh, Matheus ^{[1
,3
]}

Maiza, Claire ^{[1
]}

Goossens, Joel ^{[2
]}

Raymond, Pascal ^{[1
]}

de Dinechin, Benoit Dupont ^{[3
]}

机构：

[1] Univ Grenoble Alpes, CNRS, Grenoble INP, VERIMAG, F-38000 Grenoble, France

[2] Univ Libre Bruxelles, Fac Sci, B-1050 Brussels, Belgium

[3] Kalray SA, Montbonnot St Martin, France

来源：

2020 IEEE 41ST REAL-TIME SYSTEMS SYMPOSIUM (RTSS) | 2020年

关键词：

TIME; DEPLOYMENT; SYSTEMS;

D O I：

10.1109/RTSS49844.2020.00034

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

We study the implementation of data-flow applications on multi-core processor with on-chip shared multi-banked memory. Specifically, we consider the Kalray MPPA2 processor and three applications coded using the industrial toolchain SCADE Suite. We focus on the runtime environment assuming global static scheduling, time-triggered and non-preemptive execution of tasks. Our contributions include (i) a technique to implement SCADE applications compliant with execution models inspired by PREMs (PRedictable Execution Models), (ii) an exhaustive comparison of three execution models with and without isolation, and finally (iii) guidelines for predictable implementation of a data-flow application on multi-core processors with shared on-chip memory.

引用

页码：283 / 295

页数：13

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