Reconfigurable and area-efficient architecture for symmetric FIR filters with powers-of-two coefficients

This paper presents a new reconfigurable and area-efficient architecture for symmetric FIR filters with powers-of-two (PT) coefficients (2PFIR filters). The proposed architecture is based on the general-purpose digital signal processor (DSP) architecture. The synthesis results show that the proposed architecture is more area-efficient than the normal architecture in terms of gate count, maintaining reconfigurability. The use of a single shifter/adder/accumulator as an arithmetic unit results in the good area efficiency of the proposed architecture.