FPGA Soft-Core Processors, Compiler and Hardware Optimizations Validated Using HOG

被引：2

作者：

Kelly, Colm ^{[1
]}

Siddiqui, Fahad Manzoor ^{[2
]}

Bardak, Burak ^{[2
]}

Wu, Yun ^{[2
]}

Woods, Roger ^{[2
]}

Rafferty, Karren ^{[2
]}

机构：

[1] Thales, Belfast, Antrim, North Ireland

[2] Queens Univ, Belfast, Antrim, North Ireland

来源：

APPLIED RECONFIGURABLE COMPUTING, ARC 2016 | 2016年

基金：

英国工程与自然科学研究理事会;

关键词：

FPGA; Memory; Image processing; HOG;

D O I：

10.1007/978-3-319-30481-6_7

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

There is demand for an easily programmable, high performance image processing platform based on FPGAs. In previous work, a novel, high performance processor - IPPro was developed and a Histogram of Orientated Gradients (HOG) algorithm study undertaken on a Xilinx Zynq platform. Here, we identify and explore a number of mapping strategies to improve processing efficiency for soft-cores and a number of options for creation of a division coprocessor. This is demonstrated for the revised high definition HOG implementation on a Zynq platform, resulting in a performance of 328 fps which represents a 146 % speed improvement over the original realization and a tenfold reduction in energy.

引用

页码：78 / 90

页数：13

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