Fast and Scalable Thread Migration for Multi-Core Architectures

Heterogeneous computing is a promising approach to tackle the thermal, power and energy constraints posed by modern desktop and embedded computing systems. However, by also allowing the migration of application threads to the most appropriate cores, significant performance gains and energy efficiency levels can also be attained. Nevertheless, the considerably large overheads usually imposed by software-based thread migration procedures only allow exploiting migrations at a coarse-grained level, thus limiting the effectiveness of using such techniques. Accordingly, this paper proposes a fast and efficient hardware-based thread migration mechanism that can be easily plugged-in into any core architecture. To minimize the thread migration overhead and latency, the proposed approach considers both soft-and hard-migration procedures, and adopts a conventional "most recently used" prediction scheme to identify the cache blocks that should be migrated along with the thread context. Experimental results show that the proposed scheme is lightweight and requires limited hardware resources, while allowing to attain migration latencies below 100 clock cycles and to reduce post-migration overheads in up to 60%, making it particularly appropriate for exploiting short-lived application phases.