Energy Efficient, Scalable and Dynamically Reconfigurable FFT Architecture for OFDM Systems

FFT is the most compute intensive operation that critically affects the OFDM system performance. In order to support the various OFDM standards, a scalable and reconfigurable FFT architecture is necessary. This paper presents an energy efficient and scalable FFT architecture, which can be dynamically reconfigured to adapt to specifications of different standards. The proposed architecture is based on Radix-4(3) algorithm and uses a parallel-pipelined unrolled architecture. The proposed architecture can be scaled to support FFTs of sizes upto 64K points. As a proof of concept, FFT architecture for computation of FFTs of sizes 64 to 4K point has been implemented in UMC 65nm 1P10M CMOS process with a maximum clock frequency of 125 MHz and area of 1.05mm(2). The power consumption at 40 MHz is 33.5mW for the computation of 4K point FFT. Energy efficiency (FFTs per unit of energy) of the proposed architecture is 1176 for 1K point, 584 for 2K point and 291 for 4K point FFTs at 40 MHz. The proposed architecture shows better performance in terms of scalability and energy efficiency when compared to existing implementations.