Fpga I mplementation of block truncation coding algorithm for gray scale and color images

This paper presents a Field Programmable Gate Array (FPGA) implementation for Video compression using Block Truncation Coding (BTC) image compression technique [1]. The implementation exploits the inherent parallelism of the BTC algorithm to provide efficient algorithm-to-architecture mapping. The implementation is shown for gray scale images and promoted to color ones. The Xilinx VirtexE BTC implementation has shown to provide about 23.4 x 10(6) of pixels per second which is about 3500 times faster than an Intel Pentium III 550 MHz processor.