A new architecture of UHF RFID digital receiver for SoC implementation

A new architecture of UHF (Ultra High Frequency) RFID (Radio Frequency Identification) digital receiver for SoC (System-on-Chip) implementation is presented in this paper. For the system requirements, the design uses a unique two-stage correlation algorithm to estimate the frequency of the received data which may have large frequency deviation and also to achieve fast data decoding. Considering the single chip integration, we optimize the implementation for both low hardware cost and quick response. The function of the design is verified through FPGA implementation on Altera StratixII EP2S60 with great performance and its chip design will use the SMIC 0.18um process along with other parts of the UHF RFID Interrogator chip.