Modelling systemC process behavior by the UML method state machines

被引:0
|
作者
Riccobene, E [1 ]
Scandurra, P [1 ]
机构
[1] Univ Catania, Dipartimento Matemat & Informat, I-95125 Catania, Italy
关键词
D O I
暂无
中图分类号
TP31 [计算机软件];
学科分类号
081202 ; 0835 ;
摘要
We describe the SystemC Process State Machines that we have defined, as a variation of the UML method state machines, to model the behavior of reactive processes of the SystemC language. They are part of a complete UML 2.0 profile for SystemC that we have developed to improve the SoC (System on a Chip) design flow in order to provide a modelling framework which allows high-level designing SoC components in the style of UML using the SystemC design primitives.
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页码:112 / 121
页数:10
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