All-memristive Spiking Neural Network Circuit Simulator

In this paper we present a circuit-level simulation test bed for an all-memristive spiking neural network (MSNN), composed of synapses and leaky integrate-and-fire (LIF) neuron circuits. As recently proposed, an all-memristive neural network can be designed using volatile diffusion memristors as part of the LW neuron, and non-volatile drift memristors as synaptic elements. The cognitive performances of our MSNN are demonstrated by the implementation of the spike timing dependent plasticity (STDP) learning rule. Starting from a circuit-level memristive neuron model which incorporates volatility, and a synaptic memristive array, a simple MSNN circuit simulator is designed and its performances are discussed.