Exploration of the potential performance of polycrystalline silicon-based active matrix flat-panel imagers incorporating active pixel sensor architectures

Conventional active matrix flat-panel imagers (AMFPIs), employing amorphous silicon (a-Si:H) semiconductors, are based on a relatively simple pixel architecture, commonly taking the form of a single, thin-film transistor (TFT) coupled to a pixel storage capacitor. Although this semiconductor-architecture combination has led to the successful creation of x-ray imagers for many applications, a variety of significant performance limitations related to DQE, frame rate and charge trapping have also become apparent. While prospects for designing solutions to these restrictions based on a-Si:H TFTs are uncertain, progress in the development of high-quality polycrystalline silicon (poly-Si) TFTs is opening up new possibilities for large area x-ray imager design. Recently, initial prototype imagers have been developed using poly-Si TFTs in the form of 1-stage and 2-stage pixel amplifiers - circuit architectures that can generally be referred to as active pixel sensors (APS). The insight gained from empirical evaluations of such prototypes, coupled with theoretical studies, can inspire increasingly sophisticated APS architectures that overcome the limitations, while preserving the advantages, of conventional AMFPIs. In this paper, cascaded systems analysis and circuit simulation are used to explore potential performance improvements enabled by APS architectures based on poly-Si TFTs. These studies suggest that it is possible to achieve significant improvements in DQE at low exposures or very small pixel sizes, higher maximum frame rates, and reduced charge trapping effects through implementation of such architectures.