Design and performance evaluation of an adaptive cache coherence protocol

被引:3
|
作者
Hong, WK [1 ]
Kim, NH [1 ]
Kim, SD [1 ]
机构
[1] Yonsei Univ, Dept Comp Sci, Parallel Proc Syst Lab, Seoul 120749, South Korea
关键词
D O I
10.1109/ICPADS.1998.741017
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
In shared-memory multiprocessor systems, the local caches which are used to tolerate the performance gap between processor and memory cause additional bus transactions to maintain the coherency of shared data. Especially coherency misses and data traffic due to spatial locality and false sharing have a significant effect on the system performance. In this approach, an adaptive cache coherence protocol based on the sectored cache is introduced. It determines the size of a block to be migrated or invalidated dynamically depending on the transfer mode so that it can exploit the spatial locality and reduce useless data traffic due to false sharing at the same time. This protocol is evaluated via event driven simulation and its results show 58% decrease in the data traffic and 45% decrease in the cache miss ratio. Thus, the adaptive cache coherence protocol provides about 56% improvement in the execution time.
引用
收藏
页码:33 / 40
页数:8
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