Energy-efficient embedded system design at 90nm and below - A system-level perspective

被引：0
|
作者：
Ishihara, Tohru [1 ]
机构：
[1] Kyushu Univ, Syst LSI Res Ctr, Sawara Ku, 3-8-33 Momochihama, Fukuoka 8140001, Japan
来源：
HIGH-PERFORMANCE COMPUTING | 2008年 / 4759卷
关键词：
energy estimation; energy characterization; nanometer technology; leakage power; cache memory; compiler optimization; embedded system;
D O I：
暂无
中图分类号：
TP301 [理论、方法];
学科分类号：
081202 ;
摘要：
Energy consumption is a fundamental barrier in taking full advantage of today and future semiconductor manufacturing technologies. This paper presents our recent research activities and results on estimating and reducing energy consumption in nanometer technology system LSIs. This includes techniques and tools for (i) estimating instantaneous energy consumption of embedded processors during an application execution, and (ii) reducing leakage energy in instruction cache memories by taking advantage of value-dependence of SRAM leakage due to within-die V-th variation.
引用
收藏
页码：452 / +
页数：2
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