共 50 条
- [1] Supporting timing analysis of vehicular embedded systems through the refinement of timing constraints [J]. Software & Systems Modeling, 2019, 18 : 39 - 69
- [2] Supporting timing analysis of vehicular embedded systems through the refinement of timing constraints [J]. SOFTWARE AND SYSTEMS MODELING, 2019, 18 (01): : 39 - 69
- [4] Refinement of UML/MARTE Models for the Design of Networked Embedded Systems [J]. DESIGN, AUTOMATION & TEST IN EUROPE (DATE 2012), 2012, : 1072 - 1077
- [5] Embedded systems architecture: Evaluation and analysis [J]. QUALITY OF SOFTWARE ARCHITECTURES, 2006, 4214 : 145 - +
- [6] On Validation of Simulation Models in Timing Analysis of Complex Real-Time Embedded Systems [J]. 2010 IEEE CONFERENCE ON EMERGING TECHNOLOGIES AND FACTORY AUTOMATION (ETFA), 2010,
- [8] A framework for interactive analysis of timing constraints in embedded systems [J]. FOURTH INTERNATIONAL WORKSHOP ON HARDWARE/SOFTWARE CO-DESIGN (CODES/CASHE '96), PROCEEDINGS, 1996, : 44 - 51
- [9] A Framework for Compositional Timing Analysis of Embedded Computer Systems [J]. 2015 IEEE 17TH INTERNATIONAL CONFERENCE ON HIGH PERFORMANCE COMPUTING AND COMMUNICATIONS, 2015 IEEE 7TH INTERNATIONAL SYMPOSIUM ON CYBERSPACE SAFETY AND SECURITY, AND 2015 IEEE 12TH INTERNATIONAL CONFERENCE ON EMBEDDED SOFTWARE AND SYSTEMS (ICESS), 2015, : 1001 - 1004
- [10] Embedded program timing analysis based on path clustering and architecture classification [J]. 1997 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN - DIGEST OF TECHNICAL PAPERS, 1997, : 598 - 604