Software MPEG-2 video decoder on a 200-MHz, low-power multimedia microprocessor

This paper presents a low-power, 32-bit RISC microprocessor with a 64-bit "single-instruction multiple-data" multimedia coprocessor, V830R/AV, and its MPEG-2 video decoding performance. This coprocessor basically performs multimedia-oriented four 16-bit operations every clock, such as multiply-accumulate with symmetric rounding and saturation, and accelerates computationally intensive procedures of the video decoding; an 8x8 IDCT is performed in 201 clocks. The processor employs the Concurrent Rambus DRAM interface, and facilities for controlling cache behaviors explicitly by software to speed up enormous memory accesses necessary to motion compensation. The 200-MHz V830R/AV processor with the 600-Mbyte/sec. Concurrent Rambus DRAMs decodes MPEG-2 MP@ML video in realtime (30 frames/sec.).