Efficient Implementation of AES S-box in LUT-6 FPGAs

被引：0

作者：

Nadjia, Anane ^{[1
]}

Mohamed, Anane ^{[2
]}

机构：

[1] CDTA, Algiers, Algeria

[2] ESI Ecole Natl Super Informat, Algiers, Algeria

来源：

2015 4TH INTERNATIONAL CONFERENCE ON ELECTRICAL ENGINEERING (ICEE) | 2015年

关键词：

AES; SubBytes; S-Box; LUTs;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Advanced Encryption Standard (AES) is a symmetric cryptographic algorithm used for protecting data. Designing efficient hardware architecture for AES with small hardware resource usage is a challenge. AES uses different data transformations and the most expensive one, in terms of computational resources, is the SubBytes transformation which is carried out by a Look-Up-Table (LUT) named the S-box. In this paper, an efficient implementation of the S-box on LUTs-6 of an FPGA circuit of Virtex-5 is presented. This has reduced both occupied area and execution time, where the reading time of an S-Box is that of one slice.

引用

页码：56 / +

页数：4

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