A novel specification model for IP-based design

The proposed specification method denoted as hierarchical CoDesign Model allows a hierarchical system level specification of distributed embedded systems including both definition and reuse of IP cores. Input/Output Relations are introduced as a very general and powerful means of encapsulating internal implementation details and of describing data as well as control flow information on different levels of abstraction. Two novel algorithms are proposed, which allow to derive dynamically task descriptions for the IP encapsulation as well as flat specification models for design space exploration on different levels of detail. This reduces considerably the descriptive complexity of specifications and therewith the execution times of synthesis and design space exploration algorithms.