Impact of Degradation Mechanisms in Gate Stress Tests on the Hard-Switching Behavior of 1.2 kV SiC Power MOSFETs

被引：1

作者：

Boldyrjew-Mast, Roman ^{[1
]}

Balmier, Christian ^{[1
]}

Wenisch-Kober, Felix Bruno ^{[1
]}

Liu, Xing ^{[1
]}

Basler, Thomas ^{[1
]}

机构：

[1] Tech Univ Chemnitz, Chair Power Elect, Chemnitz, Germany

来源：

2022 IEEE 34TH INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES AND ICS (ISPSD) | 2022年

关键词：

gateoxide reliability; silicon carbide; SiC MOSFETs; threshold voltage drift; bias temperature instability switching behavior; input capacitance; reverse capacitance;

D O I：

10.1109/ISPSD49238.2022.9813675

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Long term stability of gate oxides is a crucial aspect for the reliability of SiC MOSFETs. In this paper the impact of gate bias driven degradation mechanisms on electrical parameters have been investigated for SiC MOSFETs with planar and trench MOS structure. Therefore, high temperature gate bias tests have been carried out. The periodically increased gate voltage until the time dependent dielectric breakdown led to an increase of the threshold voltage and to a change of the internal capacitances. To capture the behavior of the threshold voltage precisely, the hysteresis method has been applied during intermediate read-outs. Additionally, the switching behavior of the specimens has been measured in double pulse tests to analyze the impact of the shifted electrical parameters on switching losses and waveforms.

引用

页码：229 / 232

页数：4

共 47 条

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