High gain two-stage amplifier with positive capacitive feedback compensation

A novel topology for a high gain two-stage amplifier is proposed. The proposed circuit is designed in a way that the non-dominant pole is at output of the first stage. A positive capacitive feedback around the second stage introduces a left half-plane zero, which cancels the phase shift introduced by the non-dominant pole, considerably. The dominant pole is at the output node, which means that increasing the load capacitance has minimal effect on stability. Moreover, a simple and effective method is proposed to enhance slew rate. Simulation shows that slew rate is improved by a factor of 2.44 using the proposed method. The proposed amplifier is designed in a 0.18 mu m complementary metal-oxide-semiconductor process. It consumes 0.86 mW power from a 1.8 V power supply and occupies 3038.5 mu m(2) of chip area. The DC gain is 82.7 dB and gain bandwidth (GBW) is 88.9 MHz when driving a 5 pF capacitive load. Also low frequency common-mode rejection ratio and positive power supply rejection ratio are 127 and 83.2 dB, respectively. They are 24.8 and 24.2 dB at GBW frequency, which are relatively high and are other important properties of the proposed amplifier. Moreover, simulations show convenient performance of the circuit in process corners and also the presence of a mismatch.