Phase/frequency detectors for high-speed PLL applications

被引:2
|
作者
Jeon, SO [1 ]
Cheung, TS [1 ]
Choi, WY [1 ]
机构
[1] Yonsei Univ, Dept Elect Engn, Seoul 120749, South Korea
关键词
D O I
10.1049/el:19981493
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Two new phase/frequency detectors (PFDs) are proposed that can overcome the speed and jitter limitations of conventional PFD schemes. One of the proposed circuits has a reset time of 0.32 ns and the other a reset time of 0.03 ns during the phase-locked loop capture process, according to HSPICE simulation with 0.8 mu m CMOS process parameters.
引用
收藏
页码:2120 / 2121
页数:2
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