High-Level Synthesis of FPGA Circuits with Multiple Clock Domains

We consider the high-level synthesis of circuits with multiple clock domains in a bid to raise circuit performance. A profiling-based approach is used to select time-intensive subcircuits within a larger circuit to operate on separate clock domains. This isolates the critical paths of the sub-circuits from the larger circuit, allowing the sub-circuits to be clocked at the highest-possible speed. The open-source LegUp high-level synthesis tool (HLS) [1] is modified to automatically insert clock-domain-crossing circuitry for signals crossing between two domains. The scheduling and binding phases of HLS were changed to reflect the impact of multiple clock domains on memory. Namely, the block RAMs in FPGAs are dual-port, where each port can operate on a different domain, implying that sub-circuits on different domains can access shared memory provided the domains of the memory ports are consistent with the sub-circuit domains. In an experimental study, we apply multiclock domain HLS to the CHStone benchmark suite [2] and demonstrate average wall-clock time improvements of 33%.