A 0.5V 36nW 10-transistor power-on-reset circuit with high accuracy

被引:3
|
作者
You, Heng [1 ,2 ]
Yuan, Jia [1 ,2 ]
Yu, Zenghui [1 ,2 ]
Qiao, Shushan [1 ,2 ]
机构
[1] Chinese Acad Sci, Inst Microelect, Beijing, Peoples R China
[2] Univ Chinese Acad Sci, Beijing, Peoples R China
关键词
power-on-reset; brown-out-reset; low-power; high accuracy; area efficient; VOLTAGE REFERENCE;
D O I
10.1109/ISCAS51556.2021.9401482
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this paper, a low voltage high accuracy 10-transistor power-on-reset circuit with brown-out-reset function is proposed. A native NMOS current reference based architecture is proposed to get high accuracy trip-voltage with a small area and power consumption. By adjusting the number of native NMOS transistors, a stable hysteresis window is obtained. Post-layout simulation results based on SMIC 55nm CMOS process show that the trip-voltage deviation of the proposed power-on-reset circuit is only 34mV under different temperature and process corners. Also, the trip-voltage of the proposed power-on-reset circuit shows great robustness to supply ramp time. The power consumption of the proposed circuit is as low as 36nW at 0.5V. Since the proposed power-on-reset circuit consists of only 10 transistors, the area is as low as 67.5 mu m(2).
引用
收藏
页数:5
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