Dictionary-based program compression on transport triggered architectures

Program code size has become a critical design constraint of embedded systems. Large program codes require large memories, which increase the size and cost of the chip. Poor code density is a problem especially in parallel architectures where a long instruction word controls the concurrently operating hardware resources. Dictionary compression is one of the most often used compression methods to improve the code density due to its simplicity. In dictionary compression, unique bit patterns, e.g., instructions are stored into a dictionary and replaced in the program code by indices pointing to the dictionary. In this paper, dictionary compression is evaluated on transport triggered architecture, a customizable processor architecture that is particularly suitable for tailoring the hardware resources according to the requirements of the application. Obtained results indicate significant improvements in code density.