A flexible high-throughput VLSI architecture with 2-D data-reuse for full-search motion estimation

被引：0

作者：

Lai, YK

Chen, LG

Tsai, TH

Wu, PC

机构：

来源：

INTERNATIONAL CONFERENCE ON IMAGE PROCESSING - PROCEEDINGS, VOL II | 1997年

关键词：

D O I：

10.1109/ICIP.1997.638694

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper describes a data-interlacing architecture with two-dimensional (2-D) data-reuse for full-search block-matching algorithm. Based on a one-dimensional processing element (PE:) array and two data-interlacing shift-register arrays, the proposed architecture can efficiently reuse data to decrease external memory accesses and save the pin counts. It also achieves 100% hardware utilization and a high throughput rate. In addition, the same chips can be cascaded for different block sizes, search ranges, and pixel rates.

引用

页码：144 / 147

页数：4

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