A new concept for ultra-low power and ultra-high clock rate circuits

Compared with semiconductors, SFQ logic is very fast and dissipates extremely low power. But it does not approach the theoretical power dissipation associated with an SFQ switching event and single gate speed in complex circuits. For large circuits and systems, e,g., petaflops computing, we must reduce on-chip dissipation, achieve faster clocked logic operation, and increase gate density. CMOS logic dissipates the energy required to switch a transistor pair and dissipates no power between switching events. We describe a new SFQ circuit concept that mimics CMOS to achieve ultra-low power dissipation and ultra-high clock rates. This results in a physically compact, self-clocked, complementary logic (SCCL), in which clock distribution is frequency-independent. The basic element in this logic family is a simple two-junction comparator. Using TRW's 2kA/cm(2) Nb design rules, we simulated basic digital components: shift register, AND, OR, and NOT at 20 GHz. We present the simulated and measured performance.