A 4096-neuron 1M-synapse 3.8pJ/SOP Spiking Neural Network with On-chip STDP Learning and Sparse Weights in 10nm FinFET CMOS

被引：0

作者：

Chen, Gregory K. ^{[1
]}

Kumar, Raghavan ^{[1
]}

Sumbul, H. Ekin ^{[1
]}

Knag, Phil C. ^{[1
]}

Krishnamurthy, Ram K. ^{[1
]}

机构：

[1] Intel Corp, Circuits Res Lab, Hillsboro, OR 97124 USA

来源：

2018 IEEE SYMPOSIUM ON VLSI CIRCUITS | 2018年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 4096-neuron, 1M-synapse SNN in 10nm FinFET CMOS achieves a peak throughput of 25.2GSOP/s at 0.9V, peak energy efficiency of 3.8pJ/SOP at 525mV, and 2.3 mu W/neuron operation at 450mV. The SNN skips zero-valued activations for up to 9.4x lower energy. Fine-grained sparse weights reduce memory by up to 16x. On-chip STDP trains RBMs to de-noise MNIST digits and to reconstruct natural scene images with RMSE of 0.036. A 50% sparse weight MLP classifies MNIST digits with 97.9% accuracy at 1.7 mu J/classification.

引用

页码：255 / 256

页数：2

共 2 条

[1] A 4096-Neuron 1M-Synapse 3.8-pJ/SOP Spiking Neural Network With On-Chip STDP Learning and Sparse Weights in 10-nm FinFET CMOS
Chen, Gregory K.
Kumar, Raghavan
Sumbul, H. Ekin
Knag, Phil C.
Krishnamurthy, Ram K.
[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2019, 54 (04) : 992 - 1002
[2] A 3.43TOPS/W 48.9pJ/Pixel 50.1nJ/Classification 512 Analog Neuron Sparse Coding Neural Network with On-Chip Learning and Classification in 40nm CMOS
Buhler, Fred N.
Brown, Peter
Li, Jiabo
Chen, Thomas
Zhang, Zhengya
Flynn, Michael P.
[J]. 2017 SYMPOSIUM ON VLSI CIRCUITS, 2017, : C30 - C31

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