Break-through of the trade-off between on-resistance and ESD endurance in LDMOS

For the purpose of high ESD endurance and low on-resistance in LDMOS, we propose a new trench gate LDMOS. We call this structure HST-LDMOS (Hard Snapback Trench Gate LDMOS). In order to improve ESD endurance and on-resistance, the HST-LDMOS has P(+)region between the DriftN(-) and N(+)Source and trench gate. Simulation results show that the HST-LDMOS achieves the ESD endurance of 16kV/mm(2) with the specific on-resistance of 6 rectangle 6m Omega center dot mm(2). This is the best characteristic ever reported for the trade-off between on-resistance and ESD endurance. Furthermore, we will present the experimental on-resistance and snapback characteristics.