A 900MS/s 6b interleaved CMOS flash ADC

被引：11

作者：

Yu, BY ^{[1
]}

Black, WC ^{[1
]}

机构：

[1] Iowa State Univ, Dept Elect & Comp Engn, Analog & Mised Signal Design Ctr, Ames, IA 50010 USA

来源：

PROCEEDINGS OF THE IEEE 2001 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 2001年

关键词：

D O I：

10.1109/CICC.2001.929744

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 900MS/s, 6 bit, 4-way, time-interleaved flash ADC is demonstrated. The 4 on-chip ADCs share a common reference string and preamplifiers to minimize the mismatch between channels. The measured SNDR is over 31dB at 900MHz with analog input at 1.1MHz. The chip has been fabricated in a standard 0.25 mum CMOS process and occupies an active area of 2.08mm(2).

引用

页码：149 / 152

页数：4

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