Sub-1V, robust and compact 6T SRAM cell in double gate MOS technology

被引：17

作者：

Thomas, Olivier ^{[1
]}

Reyboz, Marina ^{[1
]}

Belleville, Marc ^{[1
]}

机构：

[1] MINATEC, Design & Integrat Syst Div, F-38054 Grenoble, France

来源：

2007 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11 | 2007年

关键词：

D O I：

10.1109/ISCAS.2007.378629

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

This paper proposes a sub-1V, robust and compact SRAM cell in Double Gate MOS (DGMOS) technology. The presented SRAM cell is a six transistors cell characterized by two word lines connected to the front and back gate of each access transistors, respectively. Our simulations, using a 32nm low operating power DGMOS predictive model, show excellent read/write cell stability at minimal transistor dimension. Thanks to the excellent cell stability, the proposed 6T-2WL cell is also a good candidate for low voltage applications.

引用

页码：2778 / 2781

页数：4

共 50 条

[1] Stacked 3-Dimensional 6T SRAM Cell with Independent Double Gate Transistors
Weis, Marcus
Pfitzner, Andrzej
Kasprowicz, Dominik
Emling, Rainer
Fischer, Thomas
Henzler, Stephan
Maly, Wojciech
Schmitt-Landsiedel, Doris
[J]. 2009 IEEE INTERNATIONAL CONFERENCE ON INTEGRATED CIRCUIT DESIGN AND TECHNOLOGY, PROCEEDINGS, 2009, : 169 - +
[2] Performance Comparison of 6T SRAM Cell using Bulk MOSFET and Double Gate (DG) MOSFET
Gautam, Jaya
Vishwakarma, D. K.
Kapoor, Rajiv
[J]. 2ND INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING AND INTEGRATED NETWORKS (SPIN) 2015, 2015, : 954 - 957
[3] VARIABILITY ANALYSIS OF 6T AND 7T SRAM CELL IN SUB-45NM TECHNOLOGY
Islam, Aminul
Hassan, Mohd.
[J]. IIUM ENGINEERING JOURNAL, 2011, 12 (01): : 13 - 30
[4] Performance study of Ballistic and Quasi-Ballistic on Double-Gate MOSFETs 6T SRAM cell
Martinie, S.
Jaud, M. -A.
Munteanu, D.
Thomas, O.
Le Carval, G.
Autran, J. L.
[J]. NANOTECH CONFERENCE & EXPO 2009, VOL 3, TECHNICAL PROCEEDINGS: NANOTECHNOLOGY 2009: BIOFUELS, RENEWABLE ENERGY, COATINGS FLUIDICS AND COMPACT MODELING, 2009, : 359 - +
[5] Compact 6T SRAM cell with robust Read/Write stabilizing design in 45nm Monolithic 3D IC technology
Thomas, O.
Vinet, M.
Rozeau, O.
Batude, P.
Valentian, A.
[J]. 2009 IEEE INTERNATIONAL CONFERENCE ON INTEGRATED CIRCUIT DESIGN AND TECHNOLOGY, PROCEEDINGS, 2009, : 195 - 198
[6] Read stability and write ability tradeoff for 6T SRAM cells in double-gate CMOS
Giraud, Bastien
Amara, Amara
[J]. DELTA 2008: FOURTH IEEE INTERNATIONAL SYMPOSIUM ON ELECTRONIC DESIGN, TEST AND APPLICATIONS, PROCEEDINGS, 2008, : 201 - 204
[7] Comparison of 6T and 8T SRAM Cell with Parameters at 45 nm Technology
Sharma, Joshika
Khandelwal, Saurabh
Akashe, Shyam
[J]. ADVANCES IN OPTICAL SCIENCE AND ENGINEERING, 2015, 166 : 263 - 267
[8] Design and analysis of CMOS based 6T SRAM cell at different technology nodes
Devi, Meenakshi
Madhu, Charu
Garg, Nidhi
[J]. MATERIALS TODAY-PROCEEDINGS, 2020, 28 : 1695 - 1700
[9] A comparative study of 6T and 4T SRAM cells in double-gate CMOS with statistical variation
Giraud, Bastien
Amara, Amara
Vladimirescu, Andrei
[J]. 2007 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, 2007, : 3022 - +
[10] Analysis of Static Noise Margin in 6T Sram Cell At 45 And 32 NM Technology
Upadhyay, Garima
Rajput, Amit Singh
Saxena, Nikhil
[J]. JOURNAL OF ACTIVE AND PASSIVE ELECTRONIC DEVICES, 2019, 14 (2-3): : 249 - 257

← 1 2 3 4 5 →