A hardware algorithm for computing reciprocal square root

被引：4
|
作者：
Takagi, N [1 ]
机构：
[1] Nagoya Univ, Dept Informat Engn, Nagoya, Aichi 4648603, Japan
来源：
ARITH-15 2001: 15TH SYMPOSIUM ON COMPUTER ARITHMETIC, PROCEEDINGS | 2001年
关键词：
D O I：
10.1109/ARITH.2001.930108
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A hardware algorithm for computing the reciprocal square root which appears frequently in multimedia and graphics applications is proposed. The reciprocal square root is computed by iteration of carry-propagation-free additions, shifts, and multiplications by one digit. Different specific versions of the algorithm are possible, depending on the radix the redundancy factor of the digit set, and etc. Each version of the algorithm can be implemented as a sequential (folded) circuit or a combinational (unfolded) circuit, which has a regular array structure suitable for VLSI.
引用
收藏
页码：94 / 100
页数：7
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