Design, Demonstration and Characterization of Ultra-thin Low-warpage Glass BGA Packages for Smart Mobile Application Processor

This paper presents the design, fabrication, assembly, and characterization of a fully-integrated single-chip glass BGA package at 40/80 mu m off-chip I/O pitch with multilayered wiring and through-package-vias (TPVs) at 160 mu m pitch. The designed test vehicle emulates an application processor package for smart mobile applications, and enables for the first time measurements of DC signal transmission from the die to the board, through the package, at this density and pitch. A daisy chain test die, 10 mm x 10 mm in size, was designed to emulate a logic processor chip comprising 5448 I/Os distributed in four peripheral rows at 40/80 mu m pitch and a central area array at 150 mu m pitch. The test dies were fabricated and bumped with standard Cu pillars by ASE. The glass package design included four routing layers, with blind vias (BVs) and TPVs both at 150 mu m pitch, to connect 176 I/Os to the board, with BGAs at 400 mu m pitch. Independent multi-level test structures were added for evaluation of TPV and BV yield during fabrication, as well as partial chip-and board-level interconnection yield and reliability. The TPVs in glass were achieved by a via-first process with a high-throughput plasma etching and primer drilling method. Semi-additive processes (SAP), combined with wet chemical surface treatment methods were applied for patterning of the multi-layer wiring with a minimum of 20 mu m Cu trace width at 40 mu m pitch. A fan-in fan-out finger design was implemented on the top layer for bump-on-trace chip-level interconnections. Chip assembly on glass panels was carried out by high-speed thermocompression bonding with non-conductive paste (TC-NCP) with the new high-performance APAMA chip-to-substrate (C2S) bonder by Kulicke and Soffa. Yield of each process step was evaluated through fabrication and assembly by DC electrical characterization of TPV, BV and chip-level interconnection daisy chains. Die-to-substrate interconnections were characterized, demonstrating signal transmission through the fully-integrated glass package for the first time at this I/O pitch.