Reduced Current Harmonics in the NPC Inverter with a Novel Space Vector PWM

被引：0

作者：

Pratheesh, K. J. ^{[1
]}

Jagadanand, G. ^{[1
]}

Ramchand, Rijil ^{[1
]}

机构：

[1] Natl Inst Technol, Dept Elect Engn, Calicut, Kerala, India

来源：

2015 IEEE INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING, INFORMATICS, COMMUNICATION AND ENERGY SYSTEMS (SPICES) | 2015年

关键词：

Diode Clamped Topology; Three phase Multilevel inverter; Neutral Point Clamping; Space Vector Pulse Width Modulation; switching sequence; Current harmonic Distortion; ALGORITHM;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

The three-phase three-level diode clamped inverter, due to its supreme performance compared to a two-level inverter is one of the widely used multilevel inverter topology for medium voltage, high power applications. One of the popular control strategies for these inverters is space vector pulse width modulation (SVPWM) which has superior advantages in terms of its implementation and harmonic reduction. A three-level neutral point clamped (NPC) inverter with space vector modulation is presented in this paper. Duty cycles of the inverter switches are calculated based on a two-level inverter space vector diagram. A switching sequence is proposed in this paper to reduce the Total Harmonic Distortion (THD) in the line current as well as to increase the DC bus utilization of the inverter. The current harmonics of conventional SVPWM based inverter is compared for various modulation indices with the new modulation method and the result is encouraging.

引用

页数：5

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