Reliability of HTO based high-voltage gate stacks for flash memories

被引：2

作者：

Raskin, Yosef ^{[1
]}

Salameh, Asaad ^{[1
]}

Betel, David ^{[1
]}

Roizin, Yakov ^{[1
]}

机构：

[1] Tower Semicond Ltd, IL-23105 Migdal Haemeq, Israel

来源：

MICROELECTRONICS RELIABILITY | 2007年 / 47卷 / 4-5期

关键词：

D O I：

10.1016/j.microrel.2007.01.041

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We report on the excellent reliability performance of high-voltage (HV) gate stacks comprised of a thin thermal oxide and a thicker HTO layer. Time-to-breakdown of the developed stacks exceeded corresponding values for thermal HV oxides of the same thickness. Peculiarities of current relaxation in course of electrical stress tests are interpreted by injected charge trapping in HTO and new trap generation. Charge trapping in optimized HTO is low and guarantees reliable device operation. (C) 2007 Elsevier Ltd. All rights reserved.

引用

页码：615 / 618

页数：4

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