A Pipelined Noise-Shaping SAR ADC Using Ring Amplifier

被引:2
|
作者
Lee, Juyong [1 ]
Lee, Seungjun [1 ]
Kim, Kihyun [1 ]
Chae, Hyungil [1 ]
机构
[1] Konkuk Univ, Dept Elect & Elect Engn, Seoul 05029, South Korea
基金
新加坡国家研究基金会;
关键词
analog-to-digital converter; noise-shaping; pipelined SAR ADC; pipelined noise-shaping SAR ADC; ring amplifier; filter mismatch; DB SNDR; MW;
D O I
10.3390/electronics10161968
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
In this study, a pipelined noise-shaping successive-approximation register analog-to-digital converter (PLNS-SAR ADC) structure was proposed to achieve high resolution and to be free from comparator design requirements. The inter-stage amplifier and integrator of the PLNS-SAR ADC were implemented through a ring amplifier with high gain and speed. The ring amplifier was designed to improve power efficiency and be tolerant to process-voltage-temperature (PVT) variation, and uses a single loop common-mode feedback (CMFB) circuit. By processing residual signals with a single ring amplifier, power efficiency can be maximized, and a low-power system with 30% lower power consumption than that of a conventional PLNS-SAR ADC is implemented. With a high-gain ring amplifier, noise leakage is greatly suppressed, and a structure can be implemented that is tolerant of mismatches between the analog loop and digital correction filters. The measured signal to noise distortion ratio (SNDR) is 70 dB for a 5.15 MHz bandwidth (BW) at a 72 MS/s sampling rate (Fs) with an oversampling ratio (OSR) of 7, and the power consumption is 2.4 mW. The FoM(S)(,)(SNDR) (= SNDR + 10 log(10)BW/Power) is 163.5 dB. The proposed structure in this study can achieve high resolution and wide BW with good power efficiency, without a filter calibration process, through the use of a ring amplifier in the PLNS-SAR ADC.
引用
收藏
页数:15
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