Enabling Efficient Fine-Grained DRAM Activations with Interleaved I/O

DRAM contributes a significant part of the total system energy consumption, and row activation is one of the most energy inefficient components. Prior works on fine-grained DRAM activation rely on increasing the number of local wires to avoid degrading performance, which adds area overheads. This work proposes interleaved I/O to allow data transferring from different partially activated banks to share the global I/O. The proposed DRAM architecture allows half-, quarter-, or one-eighth-page activations without changing the wires. The system performance is competitive as compared with other finegrained activation designs. For the evaluated benchmarks, an average of up to 15.7% performance improvement is achieved among all of the configurations. Furthermore, the total DRAM energy can be reduced by an average of 11.2% for halfpage, 17.2% for quarterpage, and 22.3% for one-eighth-page.