Tunable 1/f Noise in CVD Bernal-Stacked Bilayer Graphene Transistors

Low-frequency noise is a key performance-limiting factor in almost all electronic systems. Thanks to its excellent characteristics such as exceptionally high electron mobility, graphene has high potential for future low-noise electronic applications. Here, we present an experimental analysis of low-frequency noise in dual-gate graphene transistors based on chemical vapor-deposited Bernal-stacked bilayer graphene. The fabricated dual-gate bilayer graphene transistors adopt atomic layer-deposited Al2O3 and HfSiO as top-gate and back-gate dielectric, respectively. Our results reveal an obvious M-shape gate-dependent noise behavior which can be well described by a quantitative charge-noise model. The minimal area normalized noise spectral density at 10 Hz reaches as low as about 3 x 10(-10) mu m(2).Hz(-1) at room temperature, much lower than the best results reported previously for graphene devices. In addition, the observed noise level further decreases by more than 10 times at temperature of 20 K. Meanwhile, the noise spectral density amplitude can be tuned by more than 2 orders of magnitude at 20 K by dual-gate voltages.