Low-voltage fourth-order CMOS sigma-delta modulator implementation

被引：4
|
作者：
Lampinen, H [1 ]
Vainio, O [1 ]
机构：
[1] Tampere Univ Technol, Digital & Comp Syst Lab, Dept Informat Technol, FIN-33720 Tampere, Finland
来源：
ELECTRONICS LETTERS | 2001年 / 37卷 / 12期
关键词：
D O I：
10.1049/el:20010502
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A low-voltage, high-speed fourth-order sigma-delta modulator implementation is presented. The low-voltage and high-speed operation are obtained by using a novel combination of architectural features, proper circuit structure selections, specific clocking strategies, and efficient circuit optimisation algorithms. Measurement results from fabricated CMOS chip prototypes show a good match with simulations.
引用
收藏
页码：734 / 735
页数：2
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