Overcoming the mixed signal chip simulation limits of the EF anti-jitter circuit

被引：0

作者：

Underhill, Michael ^{[1
]}

Brodrick, James ^{[2
]}

机构：

[1] Underhill Res, Surrey RH7 6LL, England

[2] Toric Ltd, London NW1 6AD, England

来源：

PROCEEDINGS OF THE 2007 IEEE INTERNATIONAL FREQUENCY CONTROL SYMPOSIUM-JOINTLY WITH THE 21ST EUROPEAN FREQUENCY AND TIME FORUM, VOLS 1-4 | 2007年

关键词：

D O I：

10.1109/FREQ.2007.4319078

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The EF-AJC is a mixed signal circuit operating with GHz sawtooth waveforms and feedback time constants of a few milliseconds. Jitter has to be modeled to sub-picosecond accuracy. Conventional time-step simulation is impossible in reasonable time. The paper addresses the validity of the 'indirect' simulation methods that have to be used. The 'simulations' are compared with 500MHz results from a Fujitsu Mcro-Electronics test chip. This 90nm chip suppresses jitter by 8 times. The estimated residual jitter is less than an estimated 2 to 5ps.

引用

页码：266 / +

页数：2

共 43 条

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