Minimization of Common-Mode Voltage for Five-Phase Three-Level NPC Inverter Using SVPWM Strategy

In this paper, space vector pulse width modulation technique is proposed to reduce the common-mode voltage (CMV) of a five-phase three-level neutral point clamped inverter. The switching pulses are generated by tracking the reference vector in the complex hexagonal region. The switching state vectors are selected for switching pulse generation, which have minimum CMV level. Totally, it consists of 243 switching state vectors; in that, 116 switching states are used to minimize the CMV level and to obtain the desired output voltage levels. And no additional algorithm or techniques are required to minimize the CMV level. Also, this method uses the redundant switching state vectors, which leads to minimizing the capacitor voltage unbalancing, THD minimization and neutral current reduction in the system without making any modification from the control. So for three-level inverter, the CMV is reduced up to V-dc/6 times of input voltage; in this system, an attempt is made to reduce the CMV level below this reported value. This proposed system's results are compared with those of conventional PWM methods. The simulation and hardware results are verified using MATLAB Simulink and FPGA controller, respectively.