共 5 条
- [1] A Software-managed Approach to Die-stacked DRAM [J]. 2015 INTERNATIONAL CONFERENCE ON PARALLEL ARCHITECTURE AND COMPILATION (PACT), 2015, : 188 - 200
- [2] SELF: A High Performance and Bandwidth Efficient Approach to Exploiting Die-stacked DRAM as Part of Memory [J]. 2017 IEEE 25TH INTERNATIONAL SYMPOSIUM ON MODELING, ANALYSIS, AND SIMULATION OF COMPUTER AND TELECOMMUNICATION SYSTEMS (MASCOTS), 2017, : 187 - 197
- [3] A Cost-effective and Energy-efficient Architecture for Die-stacked DRAM/NVM Memory Systems [J]. 2018 IEEE 37TH INTERNATIONAL PERFORMANCE COMPUTING AND COMMUNICATIONS CONFERENCE (IPCCC), 2018,
- [4] CACTI-3DD: Architecture-level Modeling for 3D Die-stacked DRAM Main Memory [J]. DESIGN, AUTOMATION & TEST IN EUROPE (DATE 2012), 2012, : 33 - 38
- [5] DRIS-3: Deep Neural Network Reliability Improvement Scheme in 3D Die-Stacked Memory based on Fault Analysis [J]. PROCEEDINGS OF THE 2019 56TH ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC), 2019,