Low-power single-to-differential LNA at S-band based on optimised transformer topology and integrated ESD

A single-ended to differential low-power low-noise amplifier (LNA) designed and implemented in 0.18 mu m CMOS technology is presented. The device takes advantadge of a current reuse strategy by stacking two common-source differential transistor pair stages for minimum current dissipation, together with the design of optimised high Q differential transformers and inductors in order to minimise the impact of parasitics. The fully integrated, including ESD protection diodes, 2.1 GHz LNA consumes 1.1 mW at 1.2 V supply voltage and presents 29.8 dB gain, 4.5 dB noise figure, 221.1 dBm 1 dB compression point,-11.6 dBm input third-order intercept point and-12.3 dB input return loss performance.