A Holistic Approach to Process Co-optimization for Through-Silicon Via

被引：0
|
作者：
Ramaswami, Sesh [1 ]
机构：
[1] Appl Mat Inc, Silicon Syst Grp, Sunnyvale, CA 94085 USA
来源：
2011 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS) | 2011年
关键词：
Chemical vapor deposition (CVD); chemical-mechanical planarization (CMP); electrochemical deposition (ECD); etch; physical vapor deposition (PVD); through-silicon via (TSV);
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
As through-silicon via (TSV) technology transitions from development to production, several opportunities exist to co-optimize processes to ensure a wide process window while meeting cost targets and manufacturing robustness. Trade-offs in the via middle, via reveal, and via last integration schemes involving etch, CVD, PVD, ECD, CMP, and wafer support systems (carrier wafers) are addressed.
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页数：3
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