FPGA-based implementation of RAM with asymmetric port widths for run-time reconfiguration

被引：4
|
作者：
Senhadji-Navarro, R. [1 ]
Garcia-Vargas, I. [1 ]
Jimenez-Moreno, G. [1 ]
Civit-Balcells, A. [1 ]
机构：
[1] Univ Seville, Dpto Arquitectura & Technol Computadores, Seville, Spain
来源：
2007 14TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-4 | 2007年
关键词：
D O I：
10.1109/ICECS.2007.4510959
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper, we present a HDL description of a RAM with asymmetric port widths which allows read and write operations with different data size. This RAM is suitable for implementing run-time reconfigurable systems in FPGA. The proposed RAM specification has been tested with different target devices.
引用
收藏
页码：178 / 181
页数：4
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