Reliable cache architectures and task scheduling for multiprocessor systems

被引：5

作者：

Sugihara, Makoto ^{[1
]}

Ishihara, Tohru ^{[2
]}

Murakami, Kazuaki ^{[3
]}

机构：

[1] Toyohashi Univ Technol, Dept Informat & Comp Sci, Toyohashi, Aichi 4418580, Japan

[2] Kyushu Univ, Syst LSI Res Ctr, Fukuoka 8140001, Japan

[3] Kyushu Univ, Dept Informat, Fukuoka 8140001, Japan

来源：

IEICE TRANSACTIONS ON ELECTRONICS | 2008年 / E91C卷 / 04期

关键词：

single event upset; SRAM; DRAM; reliability; cache architecture; task scheduling;

D O I：

10.1093/ietele/e91-c.4.410

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper proposes a task scheduling approach for reliable cache architectures (RCAs) of multiprocessor systems. The RCAs dynamically switch their operation modes for reducing the usage of vulnerable SRAMs under real-time constraints. A mixed integer programming model has been built for minimizing vulnerability under real-time constraints. Experimental results have shown that our task scheduling approach achieved 47.7 - 99.9% less vulnerability than a conventional one.

引用

页码：410 / 417

页数：8

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